IFS MEMORY IP LEAD/PRINCIPAL

Job Details:Job Description: About the Group:As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services IFS, a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can choose from including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.About the Role:Intel Foundry Services is looking for a Memory IP lead who has industry and/or Intel experience to:Hands on experience in custom memory and/or memory compiler design techniques and architectural tradeoffs like single versus dual rail, high density versus high performance, Vmin, performance, read/write assists etc.Drive end-to-end custom memory development that includes analyzing architectures for PPA, analyze existing designs through circuit simulations to improve PPA, pre-silicon validation, post-silicon test plans and driving silicon characterization to publish Si reports.Ability to contribute technically as well as lead a team.Institute memory IP QA (quality assurance) audits/checks to ensure high quality IP deliveries to IFS customers.Drive technical discussion with IFS customers and 3rd party IP supplier engagements.Drive and influence RFI/RFQ/SOW decisions and reviews, memory IP design reviews and QA audits with foundry and 3rd party IP suppliers.Strong familiarity with memory characterization and EDA view generation (timing, noise, power, Mbist etc.) process.This individual will socialize and drive decisions with IFS stakeholders by synthesizing memory IP requirements from customers, gather market intelligence and work with internal and 3rd party IP suppliers to develop a rich platform portfolio on leading-edge foundry technologies to enable customer products and address market segments with best-in-class PPAC (power, performance, area, cost) IPs.The ideal candidate should exhibit the following behavioral traits:Service mindset with a focus on quality solutions, drive velocity of execution and thrive in solving complex problems for customers and suppliers.Skills with ecosystem partnership collaborations.Experience and expertise:7+ years' experience in designing custom memory or compilers on leading edge technologies with silicon validated IPs in high volume products. 7+ years' experience in technical problem solving.Applications and solutions engineering mindset to enable IFS customer enablement with foundry memory compiler portfolio.Expertise in memory types like SP, 2P, P2P, MP, ROM etc.Strong understanding of bitcell/technology offerings and their trade-off and advanced memory techniques like read/write assists, power gating features, single/dual rail etc.Familiarity with EDA tool suite used for IP development and signoff, IP characterization and EDA view generation, IP QA for customer collateral readiness.Bring industry standard BKMs to enable PPAC optimized memory solutions.Proven track record of designing memory IP, delivery, and integration into product SOC for HVM.Highly proficient in memory circuit design techniques and trade-offsAbility to synthesize customer memory requirements into specifications that are best in class for PPAC.Ability to be customer focused and obsessed in driving technical engagements and meeting IP delivery milestones with high quality collaterals.Experience working with multiple foundry technologies is a plus.In-depth knowledge /experience with Intel technology is a strong plus.Excellent project and program management skills to mitigate risk and drive execution to meet customer schedule commitments.Strong communication and presentation skills to executive management.Qualifications:MS degree with at least 10+ years additional experience, or a PhD with 3+ years additional experience, in Electrical Engineering or Physics, or related field.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, San Diego, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first Open System Foundry model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here: Annual Salary Range for jobs which could be performed in US, California:$186,760.00-$299,166.00Salary range dependent on a number of factors including location and experience.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.SummaryLocation: US, Oregon, Hillsboro; US, California, San Diego; US, California, Folsom; US, California, Santa Clara; US, Texas, Austin; US, Arizona, PhoenixType: Full time